The present invention relates to computer system including a program supervisory device for controlling a data bus of a CPU of a microprocessor or the like of the computer system.
FIG. 1 illustrates a conventionally used program supervisory device of the type mentioned above. In FIG. 1, reference numeral 1 denotes the CPU of a microprocessor or the like, 2 denotes an address bus to which the output of the CPU is applied, 3 denotes a switch or a latch-type register, 4 denotes a data bus to which the output of the register 3 is applied, 5 denotes a comparator for performing address comparison, 6 denotes a signal line for applying the output of the comparator 5 to the CPU 1, 7 denotes a memory in which an operating program and data for the CPU 1 are stored, and 8 denotes a system data bus used for data transfer between the CPU 1 and the memory 7.
The operation of this device will now be described. In order to execute instructions, the CPU 1 first applies an address to the memory 7 through the address bus 2. In an ordinary operation, the memory 7 system outputs an instruction code onto the system data bus in response to a request from the CPU 1. The instruction code then causes the CPU 1 to carry out the corresponding designated operation. The CPU 1 continuously and sequentially carries out such operations.
When it is desired to stop the execution of a program at a specific address, that address is written into the register 3. The address at which program execution is to be halted (hereinafter referred to as a break point address) is applied to the data bus 4. The comparator 5 continuously compares the contents of the address bus 2 and the data bus 4 with each other, and upon the detection of coincidence between the data words on the wo buses, the comparator 5 produces a coincidence signal on the signal line 6 to inform the CPU 1 of the fact of coincidence. Upon the reception of this coincidence signal, the CPU 1 stops the program then under execution.
Arranged in the manner as described above, the conventional program supervisory device as disadvantages in that the addresses of a program being executed by the CPU 1 do not coincide with the addresses used for instruction fetching in the case where the CPU 1 has an instruction advance reading function (for example in an Intel Corp. type M5L8086S microprocessor), hence making it impossible to generate a break point signal at a designated address. Further, even if a software interrupt instruction is issued, it is impossible to rewrite the contents at a designated address of a program in a ROM base, and it is also impossible to stop a program at a desired address.